Modern integrated circuits are becoming smaller, more dense, and faster. The increased density and speed of integrated circuits (chips) has resulted in chips with internal operating frequencies far higher than external operating frequencies. For example, the internal clock frequencies of some microprocessors have increased from a few megahertz (MHz) 20 years ago, to over one gigahertz (GHz) today, while external operating frequencies have generally stalled at less than 100 MHz.
The overall performance of some integrated circuits is reduced because of lower external operating frequencies. For example, an integrated circuit that transmits or receives a significant amount of data may have to “stall” internal operations while the external interface “catches up” with the faster internal circuitry.
Reliable high speed data transmission between integrated circuits is hampered in part by phase jitter and clock skew as data signals and clock signals travel between the integrated circuits. Circuits have been developed to “recover” the phase of clock signals as they are received by integrated circuits. Clock recovery aids in the alignment of the phase of the clock signal with a received data signal in order to increase reliability of the received data. See, for example, Stephanos Sidiropoulos and Mark A. Horowitz, “A Semidigital Dual Delay Locked Loop,” IEEE Journal of Solid State Circuits, Volume 32, No. 11, November 1997. As the external operating frequencies continue to increase, finer phase control in clock recovery circuits can further increase reliability.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and apparatus to provide fine phase control in clock recovery circuits.